NAND type flash memory is one of two types of flash memory technologies (the other being NOR) that are currently available. NAND type flash memory is best suited for use in devices requiring high capacity data storage. The architecture of NAND type flash memory provides significantly more storage space, and offers faster erase, write and read capabilities as compared to NOR type flash memory. NAND arrays include a large number of strings of memory cells that are connected through one or more select transistors between individual bit lines and a reference potential. FIG. 1 shows a pair of conventional NAND memory cell strings 100, such as are used in the aforementioned NAND arrays.
In particular, FIG. 1 shows the programming conditions for programming a memory cell of a conventional NAND memory cell string. Referring to FIG. 1, NAND memory cell string pair 100 includes programmed memory cell 101 and program inhibited cell 103. Programmed memory cell 101 is programmed when a programming voltage is applied to the gate terminal of both programmed memory cell 101 and program inhibited cell 103. As part of the programming pass transistors 105, 107, 109 and 111 operate to pass a program voltage to programmed memory cell 101 (e.g., zero volts in the FIG. 1 example). A problem arises when it is desired to program one memory cell on a word line without programming other memory cells located under the same word line, for example, when it is desired to program programmed memory cell 101 and not program inhibited memory cell 103. Because the programming voltage is applied to all memory cells located under a word line that it is applied to, an unselected memory cell (a memory cell that is not intended to be programmed) on the word line may become inadvertently programmed (such as, for example, program inhibited memory cell 103). The unintentional programming of the unselected memory cell is referred to as program disturb.
In general, program disturb is used to describe any unwanted threshold voltage shift, either in the positive or negative direction, which can occur during a programming operation and is not necessarily limited to memory cells associated with a selected word line. A conventional methodology for preventing program disturbs is called channel self-boosting. Channel self-boosting involves a boosting of the “potential” or voltage of the channel regions of memory cells on unselected bit lines through the capacitive coupling of the channels with pass voltages that are applied to the gates of the memory cells. Accordingly, even though a high voltage is applied to the word line associated with a non-selected memory cell, the potential difference between the high voltage applied to the word line and the channel potential is not sufficient to cause electron tunneling through the oxide to the floating gate (because of the boosted channel voltage). Consequently, program disturb is prevented.
In conventional self-boosting applications the uniformity of the channel voltage Vch of the program inhibited memory cell is dependent on the program/erase pattern of the associated memory cell string. It should be appreciated that in such applications Vch may not be uniformly distributed if any memory cell in the memory cell string is programmed. Moreover, in pre-charging applications, Vch as measured on the drain side of the program inhibited memory cell channel may be higher than Vch as measured on the source side of the program inhibited memory cell channel. Accordingly, memory cells on the source side of the program inhibited memory cell are vulnerable to program disturbs. In addition, the voltage difference between Vch as measured on the source and drain sides of the program inhibited memory cell channel can become greater as Vd rises. Several channel self-boosting methodologies for preventing program disturb are described herein below with reference to FIGS. 2A-10C.
FIG. 2A shows programming conditions for a memory cell string employing a conventional local self-boosting (LSB) programming methodology. Referring to FIG. 2A, during programming operations, a programming voltage Vpgm is applied to the gate of program inhibited memory cell 201 and zero volts is applied to the gates of isolating memory cells 207 and 209 that are located adjacent to program inhibited memory cell 201. Moreover, zero volts is applied to the source select gate 203 and three volts is applied to the drain select gate 205 of memory cell string 200. It should be appreciated that the application of zero volts to the gates of memory cells 207 and 209 turns off these memory cells in unselected bit lines and thus isolates program inhibited memory cell 201 such that Vch for program inhibited memory cell 201 is dependent on the programming voltage Vpgm that is applied to its gate. It should be appreciated that the application of the programming voltage Vpgm to the gate of program inhibited memory cell 201 boosts the channel potential Vch of program inhibited memory cell 201 such that the potential difference between the Vpgm and Vch is not sufficient to cause electron tunneling. Thus, in this manner program disturb at program inhibited memory cell 201 can be prevented.
As shown in the FIG. 2C schematic, and as discussed above, using LSB, program inhibited memory cell 201 is isolated from memory cells on its source and drain sides. Moreover, memory cells on its drain side are erased and memory cells on the source side of the program inhibited memory cell 201 are programmed to either one or zero. This is contrasted with other conventional boosting methodologies such as is shown in FIG. 2B, where there is no isolating of the program inhibited memory cell (e.g., 201 in FIG. 2A) and where memory cells on the drain and source sides of the program inhibited memory cell have a pass voltage Vpass applied to their gates.
Referring again to FIG. 2A, conventional local self-boosting (LSB) is characterized by a sequential programming of memory cells from source to drain (e.g., bit line). This process allows zero volts to be passed from the source line to the memory cells that are to be programmed. It should be appreciated that the channel voltage of program inhibited memory cells can reach high voltages in excess of 10 volts. In addition to the structures discussed above, FIG. 2A shows word lines w10-w115 associated with respective memory cells, source line SL, bit line BL and memory cell junctions a0-a16.
FIG. 3A shows programming conditions for a NAND memory cell string 300 employing a conventional LSB programming methodology. Referring to FIG. 3A, during typical programming operations, a programming voltage is applied to the gate of program inhibited memory cell 301. In addition, zero volts is applied to the gate of the source side isolating memory cell 307 that is adjacent to program inhibited memory cell 301 and two volts is applied to the gate of the drain side isolating memory cell 309 that is adjacent to program inhibited memory cell 301. It should be appreciated that during programming operations zero volts is applied to the source select gate 303 and three volts is applied to the drain select gate 305 of memory cell string 300. As shown in FIG. 3A, memory cells other than the adjacent isolating memory cell 309 on the drain side of program inhibited memory cell 301 are erased and have a pass voltage applied to their gates. Moreover, a pass voltage Vpass is applied to the gate terminals of memory cells other than the adjacent isolating memory cell 307 on the source side of program inhibited memory cell 301.
Drawbacks of LSB methodologies shown in FIGS. 2A and 3A as it relates to floating gate (FG)-NAND include: (1) band to band tunneling (BBT) of junction leakage, and (2) punch through (PT) channel leakage. It should be appreciated that BBT of junction leakage is likely to occur, for example, if isolating memory cell 307 is programmed, Vt is approximately three volts and Va3 (voltage at junction a3) is equal to approximately nine volts as shown in FIG. 3B. This is because the junction bias with the gate of isolating memory cell 307 at a negative potential and the drain at a relatively high positive potential (e.g., nine volts etc.) creates an intense electric field that can cause BBT. FIG. 3B shows exemplary voltage characteristics of isolating memory cell 307 (Vth=3.5 v, Vfg=−2 v, Va2=2 v, Va3=9 v and Vg2=0 v) using the aforementioned LSB methodology. Moreover, it should be appreciated that PT channel leakage can occur if isolating memory cell 307 is erased and Vt is less than zero volts for FG-NAND applications because the application of zero volts to the gate of memory cell 307 may not constitute a sufficient application of voltage to turn off the transistor associated with memory cell 307.
As it regards the LSB approach illustrated in FIG. 3A, a lower Vpass voltage may be required. The channel voltage Vch of program inhibited memory cells can be locally boosted to higher values than can be attained using boosting methodologies that do not employ isolation. However, because the local boosted capacitance is very small in such cases, charge is easily leaked. Consequently, the device is very vulnerable to junction leak.
FIG. 4A shows programming conditions for a NAND memory cell string 400 employing a conventional erased area self-boosting (EASB) programming methodology. Referring to FIG. 4A, during programming operations, a programming voltage Vpgm is applied to the gate of program inhibited memory cell 401 and zero volts is applied to the gate of the source side isolating memory cell 407 that is adjacent to program inhibited memory cell 401. Furthermore, a pass voltage Vpass is applied to the gate of the drain side memory cell 409 that is adjacent to program inhibited memory cell 401. It should be appreciated that zero volts is applied to the source select gate 403 and Vcc is applied to the drain select gate 405 of memory cell string 400. As shown in FIG. 4A, memory cells 411 on the drain side of program inhibited memory cell 401 are erased. Moreover, a pass voltage Vpass is applied to the gate terminals of memory cells 411 located on the drain side of program inhibited memory cell 401 and memory cells 413 located on the source side of program inhibited memory cell 401.
Referring again to FIG. 4A, as is shown therein, program inhibited memory cell 401 is isolated only from the source side of the channel rather than from both the source and drain sides as is done in LSB. In EASB, the value of Vpass is related to disturbs as it is in some other conventional boosting methodologies (such as discussed with reference to FIG. 1A). Moreover, in EASB, Vch depends on Vpass much more than it does in LSB. It should be appreciated that EASB generates a lower channel voltage Vch of the program inhibited memory cell 401 overall as compared to LSB, and thus provides smaller (GIDL) gate induced drain leakage and exhibits less variation of Vch.
In addition, as compared to LSB, EASB provides a larger channel capacitance and larger total junction capacitance which provides the memory cell structure with greater protection against junction leakage. Moreover, as compared to LSB, EASB has a boosting voltage that is less dependent on the programming status of memory cells, exhibits lower junction stress and has an efficiency that is less degraded by use of a buffered boosting scheme (see buffering methodologies discussed below with regard to FIGS. 7A and 7B).
FIG. 4B shows typical voltage characteristics of isolating memory cell 407 (Vth=3.5 v, Va2=2 v, Va3=7 v and Vg2=0 v) during programming operations where isolating memory cell 407 is programmed. As shown in FIG. 4B the voltage at junction a3 (which is one of the junctions a1-a16 shown in FIG. 4A) is reduced as compared to LSB and thus “gated diode” or BBT leakage is reduced.
FIG. 5 shows intrinsic capacitances associated with LSB operations upon which quantifications (such as are provided below) of BBT and PT junction leak for conventional LSB operations can be based. FIG. 5 shows gate-source capacitance Cgs, gate-drain capacitance Cgd and body bias capacitance Cdb of transistors that are a part of a memory cell string where LSB is being employed. In the computations provided below, Cgs=Cgd=0.29 fF/um and Cdb=0.12 fF/um at three volts. Referring to FIG. 5, as it regards LSB boosting:
Discharge due to BBT at Vdb=6 v and Vg=0 v for erased memory cell:CV/Ileak=2*(0.29+0.12)fF/um*1V/nA/um=0.81 uS/1V.
Discharge due to PT at Vds=3 v and Vg=0 v for erased memory cell:CV/Ileak=2*(0.29+0.12)fF/um*1V/nA/um=0.81 uS/1V.
It should be appreciated that the above computations are based on Ipt of approximately 1 nA/um and Ibbt of approximately 1 nA/um.
FIG. 6 shows intrinsic capacitances associated with EASB operations upon which quantifications of BBT and PT junction leak for conventional EASB operations (such as are provided below) can be based. FIG. 6 shows gate-source capacitance Cgs, gate-drain capacitance Cgd and body bias capacitance Cdb of transistors that are a part of a memory cell string where EASB is being employed. In the computation provided below, Cgs=Cgd=0.29 fF/um and Cdb=0.12 fF/um at three volts. Referring to FIG. 6, as it regards EASB boosting:
Discharge due to BBT at Vdb=6 v and Vg=0 v for erased memory cell:CV/Ileak=n*(0.29+0.12)fF/um*1V/1 nA/um=22.4 uS/1V
Discharge due to PT at Vds=3 v and Vg=0 v for erased memory cell:CV/Ileak=n*(0.29*2+0.12)fF/um*1V/1 nA/um=22.4 uS/1V
It should be appreciated that the above computations are based on an Ipt of approximately 1 nA/um and an Ibbt of approximately 1 nA/um where n is equal to the number of transistors on the drain side of the programmed memory cell (Ileak can be either Ipt or Ibbt). Additionally, where n is larger, the capacity of either of the types of leakage described herein (e.g., BBT or PT) to cause program disturbs is lessened, however, the local boosting value is rendered correspondingly lower.
FIGS. 7A and 7B respectively illustrate conventional EASB and LSB approaches that employ a buffered bias design (e.g., the use of a buffering memory cell). The buffered bias approaches shown in FIGS. 7A and 7B use a buffering memory cell that avoids the leakage problems that are exhibited in typical EASB and LSB approaches where a source side isolating memory cell is used adjacent the program inhibited memory cell. Referring to FIG. 7A, in the EASB case, during programming operations, a programming voltage Vpgm is applied to the gate of program inhibited memory cell 701A and zero volts is applied to the gate of isolating memory cell 706A located on the source side of program inhibited memory cell 701A. In addition, two to four volts is applied to the gate of buffering memory cell 707A that is located adjacent to program inhibited memory cell 701A. Furthermore, a predetermined gate voltage Vg4 is applied to the gate of memory cell 709A and a pass voltage Vpass is applied to the gates of drain side memory cell5 through drain side memory cell15 (see 711A in FIG. 7A) that are adjacent to memory cell 709A. It should be appreciated that Vcc is applied to the source select gate 703A and Vcc is applied to the drain select gate 705A of memory cell string 700A. Referring again to FIG. 7A, memory cells 711A on the drain side of program inhibited memory cell 701A are erased. Moreover, a pass voltage Vpass is applied to the gate terminal of memory cell 704A on the source side of program inhibited memory cell 701A.
Referring to FIG. 7B, in the LSB case, during programming operations, a program voltage Vpgm is applied to the gate of program inhibited memory cell 701B and zero volts is applied to the gates of isolating memory cell 706B and isolating memory cell 709B. In addition, two to four volts is applied to the gate of buffering memory cell 707B that is located adjacent to program inhibited memory cell 701B. Furthermore, a pass voltage Vpass is applied to the gates of the drain side memory cells 5 through 15 (e.g., 711B in FIG. 7B). It should be appreciated that Vcc is applied to the source select gate 703B and to the select drain gate 705B of the memory cell string 700B. Referring again to FIG. 7B, a pass voltage Vpass is applied to the gate terminals of memory cells 711B located on the drain side of program inhibited memory cell 701B and to the gate terminal of memory cell 704B located on the source side of program inhibited memory cell 701B. As is shown in FIG. 7B, memory cells 5 through 15 (e.g., 711B in FIG. 7B) located on the drain side of program inhibited memory cell 701B are erased.
It should be appreciated that the EASB plus buffered bias approach involves the boosting of two channels (memory cell2 and memory cell3). An advantage of the EASB and LSB plus buffered bias approaches of FIGS. 7A and 7B is an alleviation of the “gated diode” or leakage problem described above. A disadvantage of these approaches is a lowering of the boosting efficiency (the capacity to boost based on an applied gate voltage).
FIGS. 8A and 9A illustrate characteristics of the EASB plus buffered bias approach discussed with reference to FIG. 7A with buffering memory cell 707A erased and programmed respectively. Referring to FIG. 8A, when memory cell 707A acts as a buffering memory cell and is erased, BBT is less severe than is the case where buffering is not used. FIGS. 8B and 8C respectively show typical voltage characteristics of isolating memory cell 706A (Vth=3.5 v, Vfg=−2 v, Va2=5 v and Vg1=0 v) and buffering memory cell 707A (Vth=1 v, Vfg=−0.5 v, Va3=7 v and Vg2=4 v), during EASB plus buffered bias operation as illustrated in FIG. 8A. Referring to FIG. 9A, when memory cell 707A acts as a buffering memory cell and is programmed, BBT is less severe than is the case where buffering is not used. FIGS. 9B and 9C respectively, show the characteristics of isolating memory cell 706A (Vth=1 v, Vfg=−0.5 v, Va2=2 v and Vg1=0 v) and buffering memory cell 707A (Vth=3.5 v, Vfg=−2 v, Va2=2 v and Vg2=4 v) during EASB plus buffered bias operation as illustrated in FIG. 9A. FIGS. 8A-9C show that BBT is decreased through the use of buffering whether the buffering memory cell is programmed or erased.
FIGS. 10A-10C show exemplary boosting efficiencies attained using the aforementioned conventional boosting schemes (for Cgs=Cgd=0.29 fF/um and Cdb=0.12 fF/um at 3 volts). Referring to FIG. 10A, an EASB boosting scheme (such as discussed with reference to FIG. 4A) can provide a boost efficiency greater than 80 percent with Vd equal to three volts. Referring to FIG. 10B, an LSB boosting scheme (such as discussed with reference to FIG. 2A) can provide a boost efficiency greater than 70 percent with Vd equal to three volts. Referring to FIG. 10C, a buffered LSB boosting scheme (such as discussed with reference to FIG. 9B) can provide a boost efficiency greater than 61 percent with Vd equal to three volts.